The present invention relates to a semiconductor device, and an energy transmission device using the semiconductor device. More particularly, the present invention relates to a semiconductor device for repeatedly conducting and blocking a main current in a switching power supply unit such as an energy transmission device.
A conventional semiconductor device will now be described with reference to FIG. 6 (see, e.g., Patent Document 1: U.S. Pat. No. 4,811,075). A high breakdown voltage lateral semiconductor device is herein described as a specific example of the conventional semiconductor device. FIG. 6 is a cross-sectional view showing the structure of a conventional semiconductor device.
As shown in FIG. 6, a conventional semiconductor device 124 includes a high breakdown voltage semiconductor element 123 including a switching element 121 and a JFET (Junction Field-Effect Transistor) element 122. The semiconductor device 124 includes the following four types of electrodes: a source electrode 111; a gate electrode 112; a first drain electrode (hereinafter, referred to as “drain electrode”) 113; and a second drain electrode (hereinafter, referred to as “TAP electrode”) 114.
An N-type drift region 102 is formed at the surface of a P−-type semiconductor substrate 101. A P-type base region 103 is formed adjacent to the drift region 102 at the surface of the semiconductor substrate 101. An N+-type source region 104 is formed spaced apart from the drift region 102 at the surface of the base region 103. A P+-type base contact region 105 is formed adjacent to the source region 104 at the surface of the base region 103. A gate insulating film 106 is formed on the base region 103 between the source region 104 and the drift region 102. An N+-type first drain region 107 is formed spaced apart from the base region 103 at the surface of the drift region 102. An N+-type second drain region 108 is formed spaced apart from the first drain region 107 at the surface of the drift region 102.
A P-type first top semiconductor layer 109a is formed spaced apart from the first drain region 107 at the surface of the drift region 102 between the base region 103 and the first drain region 107. The first top semiconductor layer 109a is electrically connected to the base region 103 at a position not shown in the figure. A P-type second top semiconductor layer 109b is formed spaced apart from the first drain region 107 and the second drain region 108 at the surface of the drift region 102 between the first drain region 107 and the second drain region 108. The second top semiconductor layer 109b is electrically connected to the base region 103 at a position not shown in the figure.
The source electrode 111 is formed over the semiconductor substrate 101, and is electrically connected to the base region 103 and the source region 104. The gate electrode 112 is formed on the gate insulating film 106. The drain electrode 113 is formed over the semiconductor substrate 101, and is electrically connected to the first drain region 107. The TAP electrode 114 is formed over the semiconductor substrate 101, and is electrically connected to the second drain region 108.
First and second field insulating films 110a, 110b are formed on the first and second top semiconductor layers 109a, 109b, respectively. An interlayer film 115 is formed over the semiconductor substrate 101 with the first and second field insulating films 110a, 110b interposed therebetween.
When a voltage is applied between the drain electrode 113 and the source electrode 111 of the conventional semiconductor device, the drift region 102 near the second drain region 108 is depleted due to field effects. A voltage which is output to the TAP electrode 114 is therefore pinched off when it reaches, for example, about 50 V.
More specifically, as shown in FIG. 7, when a voltage lower than the pinch-off voltage is applied between the drain electrode 113 and the source electrode 111, a voltage which is supplied to the TAP electrode 114 is proportional to the voltage applied between the drain electrode 113 and the source electrode 111. When a voltage higher than the pinch-off voltage is applied between the drain electrode 113 and the source electrode 111, on the other hand, a voltage which is supplied to the TAP electrode 114 is equal to the pinch-off voltage. In other words, the voltage which is supplied to the TAP electrode 114 has a fixed value, and is lower than the voltage applied between the drain electrode 113 and the source electrode 111.
As described above, in the conventional semiconductor device 124, the voltage which is supplied to the TAP electrode 114 in an on state is proportional to the voltage of the drain electrode 113, as shown in FIG. 7. An on-state voltage between the drain electrode 113 and the source electrode 111 in an on state can be detected by the TAP electrode 114.
Even if a high voltage is applied to the drain electrode 113 in an off state, a voltage which is output to the TAP electrode 114 can be pinched off.
Operation of the conventional semiconductor device 124 will now be described.
When the source electrode 111 has a negative voltage and the gate electrode 112 has a positive voltage, the surface of a region which faces the gate electrode 112 with the gate insulating film 106 interposed therebetween in the base region 103 is reversed to an N-type region. A current can therefore be supplied between the drain electrode 113 and the source electrode 111 through the N-type region (on state). In other words, a current flowing between the drain electrode 113 and the source electrode 111 can be controlled by an electric field which is generated by applying a voltage to the gate electrode 112.
Even when the gate electrode 112 has the same potential as that of the source electrode 111 (off state) and a high voltage is applied to the drain electrode 113, a voltage which is output to the TAP electrode 114 can be pinched off by a depletion layer which spreads in the drift region 102 near the second drain region 108. The TAP electrode 114 can therefore be connected to a low voltage circuit (a specific example of the “low voltage circuit” is a control circuit (for example, see 144 in FIG. 8 described below) which is included in a switching power supply unit having the conventional semiconductor device.
Hereinafter, an energy transmission device using the conventional semiconductor device will be described with reference to FIG. 8 (see, for example, Patent Document 2: U.S. Pat. No. 5,285,369). A switching power supply unit is herein described as a specific example of the energy transmission device. FIG. 8 is a circuit diagram of a switching power supply unit including the conventional semiconductor device 124.
As shown in FIG. 8, the conventional switching power supply unit includes the conventional semiconductor device 124, a semiconductor integrated circuit 148, a direct current (DC) voltage source 152, and a transformer 160. The transformer 160 includes a primary winding 153, a first secondary winding 154, and a second secondary winding 157. The primary winding 153 is connected in series with the semiconductor device 124 and the DC voltage source 152. The first secondary winding 154 is connected to a load, and the second secondary winding 157 is connected to a control circuit 144. The conventional semiconductor device 124 is configured so that electric power is supplied from the first secondary winding 154 of the transformer 160 to the load, and electric power is supplied from the second secondary winding 157 of the transformer 160 to the control circuit 144.
Respective structures of the semiconductor integrated circuit 148, the DC voltage source 152, and the transformer 160 will be described below.
The semiconductor integrated circuit 148 includes the control circuit 144 and a medium breakdown voltage transistor 142 having a breakdown voltage of, for example, 100 V. The control circuit 144 uses, for example, pulse width modulation or the like to control switching of the semiconductor device 124 which switches a main current between a flowing state and a non-flowing state.
The DC voltage source 152 is formed by a diode bridge 150 and a filter capacitor 151. An alternating current (AC) power source e is supplied to the DC voltage source 152.
The transformer 160 includes the primary winding 153, the first secondary winding 154, and the second secondary winding 157. The first secondary winding 154 of the transformer 160 is connected to a diode 155 and a filter capacitor 156. The second secondary winding 157 of the transformer 160 is connected to a diode 158 and a filter capacitor 159.
Note that the semiconductor integrated circuit 148 is connected to the semiconductor device 124 through a gate electrode and a TAP electrode. The semiconductor integrated circuit 148 and the semiconductor device 124 are formed on separate semiconductor substrates.
The control circuit 144 is a low voltage circuit, and a high voltage cannot be applied to the control circuit 144. As shown in FIG. 8, the TAP electrode of a JFET element 122 and the control circuit 144 are therefore connected to each other through, for example, a resistor 143 and the medium breakdown voltage transistor 142.
The voltage of the TAP electrode is pinched off, as described above. Therefore, even if a high voltage is applied from the primary winding 153 of the transformer 160 to the drain electrode, the TAP electrode has a fixed voltage, that is, a pinch-off voltage (e.g., about 50 V). The TAP electrode can be connected to the control circuit 144, and starting electric power can be supplied to the control circuit 144.
Operation of supplying the starting electric power from the TAP electrode to the control circuit 144 upon starting (upon power-on) will now be described.
During normal operation, a voltage is induced in the second secondary winding 157 of the transformer 160 by repeated switching operation of the switching element 121. As a result, a current flows through the diode 158 and is supplied from a Vbias power supply terminal 149 to the control circuit 144. When the AC power source e is supplied, on the other hand, the switching element 121 has not been performing the switching operation. No voltage has therefore been induced in the second secondary winding 157, and no power source has been supplied to the control circuit 144.
The medium breakdown voltage transistor 142 is controlled by the control circuit 144 so as to be turned on when the voltage of the Vbias power supply terminal 149 has a predetermined value or less. Accordingly, after the AC power source e is supplied, a direct current which has generated in the DC voltage source 152 and has flown through the primary winding 153 is partially supplied from the TAP electrode of the JFET element 122 to the control circuit 144 through the medium breakdown voltage transistor 142 in an on state, whereby the control circuit 144 is started.
The switching element 121 then repeats the switching operation. As a result, a voltage is induced in the second secondary winding 157 of the transformer 160, and a current flows through the diode 158 and is supplied from the Vbias power supply terminal 149 to the control circuit 144. When the voltage of the Vbias power supply terminal 149 exceeds the predetermined value, the medium breakdown voltage transistor 142 is turned off, and the control circuit 144 operates in a steady state.
Since a low starting voltage which is required upon power-on can thus be generated by the TAP electrode, it is not necessary to provide a high breakdown voltage, high power resistor to supply electric power. As a result, interconnection is simplified, and reduction in cost and reduction in size of a power supply circuit can be achieved accordingly.